Design Principles
The stack is designed around a set of core architectural principles that guide its structure, execution, and reliability. These principles are not only conceptual but are directly reflected in the current implementation, ensuring that the system remains stable, maintainable, and scalable.
Architectural Pillars
The system architecture is structured around four primary pillars:
Decoupled Processing (Modularity): Functional logic is partitioned into independent modules (e.g.,
sensor,control,comm,logger), enabling clear separation of concerns. This modular structure supports isolated testing, simplified debugging, and seamless replacement or extension of individual components without affecting the overall system.Deterministic Task Execution: The VAIOS execution layer enforces well-defined scheduling of time-critical tasks. By maintaining consistent execution intervals (), the system ensures predictable behavior of control loops, which is essential for maintaining stability in real-time control systems.
Hardware Abstraction: The NavHAL layer provides a uniform interface to low-level peripherals such as I2C, SPI, and UART. This abstraction isolates hardware-specific implementations from higher-level logic, enabling portability across different microcontroller platforms.
State-Aware Fail-Safety: The system maintains a global system state (
sys_state_t) to track operational readiness and detect abnormal conditions. Safety checks across modules—such as RC signal validation and IMU health monitoring—enable automatic transitions to predefined failsafe states in the event of faults or signal loss.
These principles collectively ensure that the system remains modular, predictable, and robust under varying operating conditions. By embedding these design choices into the architecture, the Vayu stack achieves a balance between performance, flexibility, and reliability.
