Hardware-Software Co-design
The Vayu flight control system is developed using a hardware–software co-design approach, where the hardware platform and software architecture are designed in tandem to achieve deterministic performance, modularity, and scalability.
Figure 4.8 illustrates the layered architecture of the Vayu platform, highlighting the abstraction between the physical hardware and high-level application logic.
Rather than treating hardware and software as independent layers, the system is structured such that hardware capabilities directly inform software design decisions, and software requirements guide hardware selection and configuration.
Mapping of Hardware Resources to Software Modules
Each hardware component in the system is accessed through a corresponding software module, ensuring a clear and structured interface between physical devices and application logic.
| Hardware Component | Interface | Software Module |
|---|---|---|
| BMX160 IMU | I2C | Sensor Task |
| Barometer (BMP180) | I2C | Sensor Module |
| GPS Module | UART | Communication Module |
| RC Receiver (iBus) | UART | RC Input Module |
| PWM Outputs (ESC) | Timer | Motor Control Task |
| SD Card | SDIO | Logging Module |
This structured mapping ensures that all hardware interactions are mediated through well-defined software interfaces, enabling modular development and easier system maintenance.
Role of NavHAL
The Hardware Abstraction Layer (NavHAL) acts as the bridge between hardware and higher-level software components. It provides standardized interfaces for peripherals such as communication buses, timers, and GPIO.
By abstracting hardware-specific details, NavHAL allows the upper layers—including estimation, control, and communication modules—to operate independently of the underlying microcontroller. This enables portability across different hardware platforms without requiring significant changes to application logic.
Execution Support through Hardware Features
The hardware platform is specifically selected to support the deterministic execution model implemented by VAIOS. Key hardware features that enable this include:
Timers: Used for precise scheduling of control loops and generation of PWM signals.
Interrupts: Enable low-latency handling of sensor data and communication events.
Multiple Communication Interfaces: Allow concurrent data exchange without resource contention.
These features ensure that time-critical tasks such as sensor acquisition and control computation can be executed reliably at fixed intervals.
Design Alignment and Scalability
The co-design approach ensures that the system remains scalable and adaptable to future enhancements. For example, the addition of new sensors or communication protocols can be accommodated by extending the corresponding modules without modifying the overall architecture.
Similarly, hardware upgrades—such as transitioning to higher-performance microcontrollers—can be achieved with minimal impact on higher-level software due to the abstraction provided by NavHAL.
This tight integration between hardware and software enables the Vayu system to achieve predictable performance, efficient resource utilization, and long-term maintainability.